At the present time memories are utilized in virtually every type of electrical and electronic device to store data, e.g. information, operating instructions, etc. These memories are manufactured in a large variety of types including random access memories (RAM), read only memories (ROM), erasable/programmable memories (EPROM), electronically erasable/programmable memories (EEPROM), to name a few. Also, these various memories are manufactured using a variety of techniques and physical concepts, e.g. magnetic memories, capacitive memories, etc., which are in turn divided into active arrays and passive arrays. Further, at least some of the memories are dense enough to allow up to mega-bytes of information to be stored in a single memory module of practical size.
However, one major problem that is prevalent in all of the prior art memories is the fact that each bit of memory must be addressed individually by means of critically positioned conductors to read (and/or write) information from (or to) the bit. Most conventional memories are intrinsically two dimensional. The usual addressing technique for 2-D memories requires the selection of a row and column port of the array which are common to the selected bit. These rows and columns provide access to localized memory elements that are uniformly distributed in one plane. This results in hundreds of critically positioned conductors (rows, columns and I/O terminals or ports) in conjunction with the large arrays of memory bits making up a large memory. In many instances the I/O ports actually require more chip real estate or area than the array of memory bits. Because present day manufacturing techniques are limited to some type of lithography in the fabrication of the memory arrays and because the line size of the lithography is limited to submicron (generally 0.25 micron), the size of present day memories is quickly reaching an upper limit. This is primarily due to escalating fabrication costs as well as undesired quantum effects. (For example, Professor W. Maly at Carnegie Mellon showed that extrapolations of cost projections in the SIAs 1997 National Technology Roadmap for Semiconductors result in single-die costs as high as $1800 for DRAMS). Further, at room temperature, as the quantized number of electrons per gate approaches one, probability of logic error or memory error increases dramatically.
Yet, the motivation for continued miniaturization is such that all major corporations are conducting research to find nanometer-sized implementations for the logic and memory functions. In the published research literature on such nanometer-sized functions, three major problems remain: unacceptably high error rates at room temperatures; lack of cost effective mass production; and no effective I/O interface with ordinary CMOS logic.
Many or all of these problems are solved or partially solved by quantum random address memory apparatus disclosed in a copending United States Patent Application entitled "Quantum Random Address Memory", filed of even date herewith, bearing attorney docket number CR97-097, and assigned to the same assignee. However, some improvements in the fabrication of various specific components are envisioned herein.
It is a purpose of the present invention to provide new and improved quantum random address memory apparatus.
It is another purpose of the present invention to provide new and improved quantum random address memory apparatus with a mixer that is relatively simple and inexpensive to manufacture.
It is still another purpose of the present invention to provide new and improved quantum random address memory apparatus with random nano-diodes as the mixer elements.